View TDA7440D_1323558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA7440D
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
1
FEATURES
INPUT MULTIPLEXER - 4 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
Figure 1. Package
SO-28

Table 1. Order Codes
Part Number TDA7440D TDA7440D013TR Package SO-28 Tape & Reel
2
DESCRIPTION
The TDA7440D is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in Hi-Fi systems. Figure 2. Block Diagram
MUXOUTL L-IN1 4 100K 5 100K 6 100K 7 100K 0/30dB 2dB STEP 100K 2 100K 1 G VOLUME 8 INL 9
Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained
TREBLE(L) 18
BIN(L) 14 RB
BOUT(L) 15
L-IN2
L-IN3
TREBLE
BASS
SPKR ATT LEFT
27
LOUT
L-IN4
21 I2CBUS DECODER + LATCHES 22 20
SCL SDA DIG_GND
R-IN1
3
R-IN2
G
VOLUME
TREBLE
BASS
SPKR ATT RIGHT VREF
26
ROUT
R-IN3
100K 28 100K INPUT MULTIPLEXER + GAIN 10 MUXOUTR INR 11 19 TREBLE(R) 12 BIN(R) RB 13 BOUT(R) 23 CREF
D98AU883
24 SUPPLY 25
R-IN4
VS AGND
April 1999
REV. 3 1/17
TDA7440D
Figure 3. Pin Connection (Top view)
R_IN3 R_IN2 R_IN1 L_IN1 L_IN2 L_IN3 L_IN4 MUXOUTL IN(L) MUXOUT(R) IN(R) BIN(R) BOUT(R) BIN(L) 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D98AU884
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R_IN4 LOUT ROUT AGND VS CREF SDA SCL DIG-GND TREBLE(R) TREBLE(L) N.C. N.C. BOUT(L)
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 0 to 70 -55 to 150 Unit V C C
Table 3. Thermal Data
Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
Table 4. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Input Gain in (2dB step) Volume Control (1dB step) Treble Control (2dB step) Bass Control (2dB step) Balance Control 1dB step Mute Attenuation 0 -47 -14 -14 -79 100 Parameter Min. 6 2 0.01 0.1 106 90 30 0 +14 +14 0 % dB dB dB dB dB dB dB dB Typ. 9 Max. 10.2 Unit V Vrms
2/17
TDA7440D
Table 5. Electrical Characteristcs Refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified.
Symbol SUPPLY VS IS SVR RIN VCL SIN Ginmin Ginman Gstep Ri CRANGE AVMAX ASTEP EA ET VDC Amute Gb BSTEP RB Gt TSTEP CRANGE SSTEP EA VDC Amute Supply Voltage Supply Current Ripple Rejection Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution Input Resistance Control Range Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Step Mute Attenuation Control Range Step Resolution Internal Feedback Resistance Control Range Step Resolution Control Range Step Resolution Attenuation Set Error AV = 0 to -20dB AV = -20 to -56dB DC Step Mute Attenuation adjacent attenuation steps 80 Max. Boost/cut Max. Boost/cut AV = 0 to -24dB AV = -24 to -47dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max 80 +12.0 1 33 +13.0 1 70 0.5 -1.5 -2 THD = 0.3% The selected input is grounded through a 2.2 capacitor 6 4 60 70 2 80 -1 29 1.5 20 45 45 0.5 -1.0 -1.5 9 7 90 100 2.5 100 0 30 2 33 47 47 1 0 0 0 0 0 0.5 100 +14.0 2 44 +14.0 2 76 1 0 0 0 100 +16.0 3 55 +15.0 3 82 1.5 1.5 2 3 1 31 2.5 50 49 49 1.5 1.0 1.5 1 2 3 130 10.2 10 V mA dB K Vrms dB dB dB dB K dB dB dB dB dB dB dB mV mV dB dB dB K dB dB dB dB dB dB mV dB Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE
VOLUME CONTROL
BASS CONTROL (1)
TREBLE CONTROL (1)
SPEAKER ATTENUATORS
NOTE1: 1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does't reset the device. 2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
3/17
TDA7440D
Table 5. Electrical Characteristcs (continued) Refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified.
Symbol AUDIO OUTPUTS VCLIP RL RO VDC ENO Et S/N SC d VIL VIH IIN VO Clipping Level Output Load Resistance Output Impedance DC Voltage Level Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Left/Right Distortion Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0 0.4 5 0.8 AV = 0; VI = 1Vrms All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; VO = 1Vrms 95 80 0 0 106 100 0.01 0.08 1 1 2 dB dB dB dB % V V A V d = 0.3% 2.1 2 10 3.5 30 3.8 5 50 4.1 15 2.6 Vrms K V V Parameter Test Condition Min. Typ. Max. Unit
GENERAL
BUS INPUT
Figure 4. Test Circuit
5.6nF 2.2F 5.6K 100nF 100nF
MUXOUTL L-IN1 0.47F L-IN2 0.47F L-IN3 0.47F L-IN4 0.47F 7 100K 0/30dB 2dB STEP 100K 2 100K 1 6 100K 5 100K G 4 100K 8
INL
TREBLE(L) 9 18
BIN(L) 14 RB
BOUT(L) 15
VOLUME
TREBLE
BASS
SPKR ATT LEFT
27
LOUT
21 I2CBUS DECODER + LATCHES 22 20
SCL SDA DIG_GND
R-IN1 0.47F R-IN2 0.47F R-IN3 0.47F R-IN4 0.47F
3
G
VOLUME
TREBLE
BASS
SPKR ATT RIGHT VREF
26
ROUT
100K 28 100K INPUT MULTIPLEXER + GAIN 10 MUXOUTR INR 2.2F 5.6nF 11 TREBLE(R) 19 12 BIN(R) RB 13 BOUT(R) 23 CREF
D98AU885
24 SUPPLY 25
VS AGND
100nF 5.6K
100nF
10F
4/17
TDA7440D
3
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7440D audioprocessor provides 3 bands tones control. 3.1 Bass Stage Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: 1 F C = ----------------------------------------------------------------2 R1 R2 C1 C2 R2 C2 + R2 C1 + R i C1 A V = --------------------------------------------------------------R2 C1 + R2 C2 R1 R2 C1 C2 Q = ------------------------------------------------R2 C1 + R2 C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: AV - 1 C1 = ----------------------------------------2 FC Ri Q Figure 5.
Ri internal IN C1 R2
D95AU313
Q C1 C2 = ----------------------------2 AV - 1 - Q
2
AV - 1 - Q R2 = ---------------------------------------------------------------------2 C1 F C ( A V - 1 ) Q
2
OUT C2
Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground. Typical responses are reported in Figg. 14 to 17. CREF The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application requires faster power ON.
5/17
TDA7440D
Figure 6. THD vs. frequency Figure 9. Bass response
Ri = 44k C9 = C10 = 100nF (Bout, Bin) R3 = 5.6k
Figure 7. THD vs. RLOAD
Figure 10. Treble responsey
Figure 8. Channel separation vs. frequency
6/17
TDA7440D
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig. 12 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (P) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 13). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 11. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 12. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 13. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
7/17
TDA7440D
5
SOFTWARE SPECIFICATION
Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7440D A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 5.1 EXAMPLES 5.1.1 No Incremental Bus The TDA7440D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
5.1.2 Incremental Bus The TDA7440D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
8/17
TDA7440D
5.2 POWER ON RESET CONDITION Table 6.
INPUT SELECTION INPUT GAIN VOLUME BASS TREBLE SPEAKER IN2 28dB MUTE 0dB 2dB MUTE
5.3 DATA BYTES Address = 88 HEX (ADDR:OPEN). Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT SELECT INPUT GAIN VOLUME BASS NOT USED TREBLE SPEAKER ATTENUATE "R" SPEAKER ATTENUATE "L" SUBADDRESS
B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON'T CARE
In Incremental Bus Mode, the "not used" function must be addressed in any case. For example to refresh "Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent: Table 8.
SUBADDRESS VOLUME DATA BUS DATA NOT USED DATA TREBLE DATA SPEAKER_R DATA XXX10010 X0000000 XXXX1111 XXXX1111 XXXX1111 X0000010
Table 9. INPUT SELECTION
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 LSB D0 0 1 0 1 INPUT MULTIPLEXER IN4 IN3 IN2 IN1
9/17
TDA7440D
5.3 DATA BYTES (continued) Table 10. INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GAIN = 0 to 30dB
LSB D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
Table 11. VOLUME SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 X 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 X X X D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB MUTE
VOLUME = 0 to 47dB/MUTE
10/17
TDA7440D
5.3 DATA BYTES (continued) Table 12. BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
Table 13. TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 TREBLE 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
11/17
TDA7440D
5.3 DATA BYTES (continued) Table 14. SPEAKER ATTENUATE SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATION 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1 0 0 1
0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 1 X X X
0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
12/17
TDA7440D
Figure 14. PINS: 23 Figure 17. PINS: 8, 10
VS
VS 20K
VS
VS 20A
CREF 20K
MIXOUT
GND
D96AU430
D96AU426
Figure 15. PINS: 26, 27
VS
Figure 18. PINS: 19, 11
VS 20A
ROUT LOUT 24
INL INR
20A
33K
D96AU427
VREF
D96AU434
Figure 16. PINS: 1, 2, 3, 4, 5, 6, 7, 28
Figure 19. PINS: 12, 14
VS
VS
20A
20A
IN
100K VREF
D96AU425
44K BIN(L) BIN(R)
D96AU428
13/17
TDA7440D
Figure 20. PINS: 13, 15 Figure 22. PIN: 20
VS 20A
20A SCL
44K BOUT(L) BOUT(R)
D96AU429
D96AU424
Figure 21. PINS: 18, 19
Figure 23. PIN 21
VS
20A
20A TREBLE(L) TREBLE(R) 50K
SDA
D96AU433
D96AU423
14/17
TDA7440D
Figure 24. SO-28 Mechanical Data & Package Dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO-28
8 (max.)
15/17
TDA7440D
Table 15. Revision History
Date January 2004 June 2004 Revision 1 3 First Issue Modified the style-sheet in compliance with the last revision of the "Corporate Technical Pubblications Design Guide". Description of Changes
16/17
TDA7440D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
17/17

▲Up To Search▲

Price & Availability of TDA7440D

	To Download TDA7440D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .